Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices include integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits. One objective of the semiconductor industry is to continue shrinking the size of the circuits. However, as cell size of the circuits is scaled down with advances in the technology node, congestion in the M1 design becomes challenging. In particular, enabling a logic cell library without an improvement in resolution (e.g., use of extreme ultraviolet (EUV)) makes M1 design in a given cell track library (e.g., 9 track) difficult.
As illustrated in FIG. 1, a dummy gate structure is regularly used to define a shallow trench isolation (STI) region. In particular, plural gate structures, for example 101a, 101b, are formed over a substrate 100. Gate structure 111 is a dummy gate structure, used to define a STI region 102 at an edge 103 of a cell region. A cavity 110 is formed adjacent the dummy gate structure 111. A cavity 104 is created in the real gate structures 101a, 101b by etching through a dielectric layer 105 and interlayer dielectrics 109 and cap formed between sidewall spacers 106, 107 of the real gate structures 101a, 101b. A cap is removed during this etching to produce recesses 113 in the real gate structures 101a, 101b between sidewall spaces 106, 107. A cavity 110 is formed adjacent the dummy gate structure 111. Gate structure 101a, 101b are formed between source/drain regions 108. The dummy gate structure 111 maintains the cap 115.
FIG. 2 illustrates a conventional integrated circuit layout with an STI region 102 disposed between two adjacent cells 201, 202. The STI region 102 is defined by dummy gate structure 111 located at an edge of cell 201, and dummy gate structure 111 located at an edge of cell 202. The M1 layer includes segments 203, 205, and 207. As illustrated, because of the congestion, the M1 layer requires three different colors for printability. Although the dummy gate structure is conventionally used to define STI regions, it does not sufficiently mitigate congestion in M1 design.
A need therefore exists for methodology to improve M1 design patterning by mitigating congestion (e.g., freeing up space) in M1 design without additional processing steps and the resulting device.